1. Field of the Invention
This invention relates to a semiconductor device wherein a semiconductor substrate and a mounting substrate are bridged by a plurality of wires to establish connection for inputting and outputting a signal, a power supply voltage and a reference voltage between them. The presenting invention relates also to a semiconductor integrated circuit or semiconductor chip having a pad arrangement which can be applied suitably to a semiconductor device of the type described.
2. Description of the Related Art
A semiconductor integrated circuit or semiconductor chip has a plurality of pads disposed at peripheral portions of a chip main face thereof for inputting and outputting signals therethrough or supplying power therethrough.
In recent years, the region of a chip main face in which pads are to be disposed is running short.
Although this arises from several causes, it seems a first cause that the wiring bonding technique cannot follow up the refinement of the semiconductor process. The pad size necessary for wire bonding depends upon the assembly technique, particularly upon the specifications of the wiring bonding apparatus and so forth. Generally, it is difficult to reduce the wire diameter and a bonding portion while assuring the reliability. On the other hand, the area of a circuit formed on a semiconductor chip is reduced significantly by process refinement. Accordingly, the progress of the process technique makes fine working of a semiconductor device possible, and even where the size of a chip which implements the same function can be reduced, the pad size cannot be reduced extremely from restrictions in the assembly technique regarding wire bonding. As a result, where a semiconductor chip of the same function is downsized, the number of pads which can be disposed at peripheral portions of the semiconductor chip decreases.
Secondly, enhancement in function and performance of a semiconductor chip makes a cause of shortage of pads.
It is demanded to build various functions in a semiconductor chip, and as a result, the number of signals to be extracted to the outside of the semiconductor chip increases. For example, as a result of increase of the bit length of an external memory bus, there is a tendency that also the number of necessary pads relating to the memory increases.
Thirdly, speeding up of an interface between semiconductor chips makes a cause of shortage of pads.
In a high speed interface, power supply noise such as power supply-ground bounce must be suppressed. To this end, a greater number of power supply voltage pads and ground pads are required. Further, for high speed signal lines, ground pads for shielding are required. Therefore, the speeding up of the interface increases the required number of pads.
Against the pad shortage caused by such various causes as described above, such a solution as flip chip mounting is available. However, the adoption of a new mounting method such as flip chip mounting gives rise to a tendency that the cost required for the mounting such as a material cost increases. Also it is demanded to elongate the life of an existing apparatus for mounting which uses wire bonding to suppress the fabrication cost as far as possible.
In order to eliminate the shortage of pads for wire bonding or in order to suppress noise, various proposals have been made regarding the pad arrangement as disclosed, for example, in Japanese Patent Laid-Open No. 2000-252363 (hereinafter referred to as Patent Document 1) and Japanese Patent Laid-Open No. 2005-252095 (hereinafter referred to as Patent Document 2).
According to the technique disclosed in Patent Document 1, at least one of a power supply voltage pad and a ground pad is provided for each signal to be inputted to or outputted from the outside using an output (IO) buffer serving as an output stage of a circuit is provided. Patent Document 1 describes that power supply noise which is generated in the output buffer can be reduced. Further, signal pads, power supply voltage pads and ground pads are disposed in a row in a direction perpendicular to the scribe line of the chip. Therefore, even if such a noise countermeasure as described above is added, the number of pads juxtaposed in directions parallel to the outer periphery of the chip does not increase. Patent Document 1 describes that, if the outer shape of a chip is expanded, then the power supply noise can be reduced while suppressing increase of the chip size and reduction of the degree of integration.
Patent Document 2 discloses a pad arrangement wherein a plurality of pads are arranged in a direction perpendicular to a peripheral edge or scribe line of a chip similarly as in Patent Document 1. Particularly, the technique according to Patent Document 2 is characterized in that such a plurality of pads as described above are formed in different wiring line layers. This characteristic makes it possible to lead out, even where a large number of output (IO) buffers are disposed in high density, a pad can be led out to a peripheral edge portion of the chip in a one-by-one corresponding relationship from each of the IO buffers.
Further, Patent Document 2 shows a view of wire bonding in a direction taken along a cross section of a chip in the FIG. 6. According to the view, a wire is bonded on the chip side to a wiring line layer at a deep position from the surface of the chip such as in the first or second wiring line layer. Further, a bonded position of a wire to the mounting substrate side is defined by providing an offset on the mounting substrate. With this configuration, the wires can be prevented from contacting with each other.